Peripheral Component Interconnect Express (PCIe) is a third generation Input Output (3GIO) system that implements a serial, switched-packet, point-to-point communication standard at the system level. PCI Express has achieved many advantages over the prior shared bus system, such as quality of service (QoS), high speed peer-to-peer communication between external devices, adaptability, and low pin counts. The basic PCI Express architecture includes a root complex, a PCI Express switch, and various external devices. In a PCIe switch, transaction layer packets are routed between requesters and completers utilizing requests generated by the requesters and completions generator by the completer in response to the request.
PCI Express standards define the transmission of transaction layer packets (TLPs) between a root complex and various endpoints connected to external devices. In standard PCIe, there is only one root complex (RC) at the top of the hierarchy and the root complex assigns addresses and requester IDs to the other functions (i.e. endpoints, bridges, etc.) of the hierarchy. In accordance with the PCIe standard, non-posted requests are routed by address and their completions are routed by requester ID.
In the case of multiple root complexes in a PCIe system, in order to route between two or more root complexes, and thus their PCIe hierarchies, non-transparent bridging is required. Non-transparent bridging is a non-standard method of translating a transaction layer packet (TLP) from one PCI Express domain to another PCI Express domain. Non-transparent bridging between two or more domains requires mapping of the address and requester ID (REQID). In non-transparent bridging only the request has its address translated because there is no address field in the completion. Additionally, both the request and the completion of the routed TLP require the translation of the REQID field.
In the case of multiple root complexes in a PCIe system, each root complex may be coupled to a PCIe switch and each of the PCIe switches may be coupled together to implement a PCIe system having multiple root complexes. The PCIe switch may be coupled together in a cascaded or tree topology, or a combination thereof. In order to accommodate multiple root complexes in one PCIe system, each of the PCIe switches must store a requester ID (REQID) table having an entry for each requester directly connected to the switch itself and for each of the requesters connected to the other downstream PCIe switches in the hierarchy. Such a configuration requires a very large lookup table, which is undesirable due to the large integrated circuit embedded memory required to store the table.
Additionally, emerging applications for solid state drives using I/O virtualization require a large number of requester IDs to be translated by a non-transparent port of a PCIe switch. The table size required to store the requester IDs for these applications is pushing the practical limits of ASIC technology. PCIe switches are often coupled together in a cascaded topological hierarchy to accommodate multiple solid state drives. In this topology, the PCIe switch that is positioned at the top of the hierarchy must store requester ID entries in the lookup table for not only locally attached endpoints, but also for all endpoints attaches to switches below in the hierarchy. As such, the required storage for the table increases as the number of cascaded PCIe switches increases to accommodate the solid state drives. This large lookup table is undesirable due to the large integrated circuit embedded memory required to store the table.
Thus, there is a need for a method and apparatus that will reduce the size of the requester ID lookup table in a PCIe switch implementing non-transparent bridging. Accordingly, what is needed in the art is an improved requester ID lookup table having a reduced number of table entries, therefore requiring a reduced amount of memory storage, for use in a PCIe non-transparent bridging switch to accommodate multiple root complexes.